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研究心得-------CPU信息的获得,比较全面的。 |
热 ★★★★ |
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研究心得-------CPU信息的获得,比较全面的。 |
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作者:闵涛 文章来源:闵涛的学习笔记 点击数:2322 更新时间:2009/4/23 18:38:05 |
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CLFLUSH bit 18 (PSN) PSN (see standard EAX=l 0000_0003h), PSN_DISABLE MSR #1 bit 17 (PSE36) 4 MB PDE bits 16..13, CR4.PSE bit 16 (PAT) PAT MSR, PDE/PTE.PAT bit 15 (CMOV) CMOVcc, if FPU=1 then also FCMOVcc/F(U)COMI(P) bit 14 (MCA) MCG_*/MCn_* MSRs, CR4.MCE, #MC bit 13 (PGE) PDE/PTE.G, CR4.PGE bit 12 (MTRR) MTRR* MSRs bit 11 (SEP) SYSENTER/SYSEXIT, SEP_* MSRs#2 bit 10 保留 bit 9 (APIC) APIC #3, #4 bit 8 (CX8) CMPXCHG8B #5 bit 7 (MCE) MCAR/MCTR MSRs, CR4.MCE, #MC bit 6 (PAE) 64bit PDPTE/PDE/PTEs, CR4.PAE bit 5 (MSR) MSRs, RDMSR/WRMSR bit 4 (TSC) TSC, RDTSC, CR4.TSD (doesn''''t imply MSR=1) bit 3 (PSE) PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb) bit 2 (DE) CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5 bit 1 (VME) CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB bit 0 (FPU) FPU 说明 说明 #1 如果PSN无效PSN 面貌标志就是0. #2 尽管Intel P6 处理器不支持 SEP,在这里仍然会虚报(真不知Intel是怎么想的). #3 APIC无效那么APIC面貌标志就是0. #4 早期AMD K5 处理器 (SSA5)会假报支持 PGE. #5 处理器确实支持 CMPXCHG8B但默认却是报告不支持. 其实这是Windows NT的一个Bug. EAX= 0000_0002h 输入 EAX=0000_0002h 得到处理器配置描述 输出 EAX.15..8 EAX.23..16 EAX.31..24 EBX.0..7 EBX.15..8 EBX.23..16 EBX.31..24 ECX.0..7 ECX.15..8 ECX.23..16 ECX.31..24 EDX.0..7 EDX.15..8 EDX.23..16 EDX.31..24 配置描述 值 说明 00h null descriptor (=unused descriptor) 01h code TLB, 4K pages, 4 ways, 32 entries 02h code TLB, 4M pages, fully, 2 entries 03h data TLB, 4K pages, 4 ways, 64 entries 04h data TLB, 4M pages, 4 ways, 8 entries 06h code L1 cache, 8 KB, 4 ways, 32 byte lines 08h code L1 cache, 16 KB, 4 ways, 32 byte lines 0Ah data L1 cache, 8 KB, 2 ways, 32 byte lines 0Ch data L1 cache, 16 KB, 4 ways, 32 byte lines 10h data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) 15h code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) 1Ah code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64) 22h code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, dual-sectored 23h code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored 25h code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored 29h code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored 39h code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored 3Bh code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored 3Ch code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored 40h no integrated L2 cache (P6 core) or L3 cache (P4 core) 41h code and data L2 cache, 128 KB, 4 ways, 32 byte lines 42h code and data L2 cache, 256 KB, 4 ways, 32 byte lines 43h code and data L2 cache, 512 KB, 4 ways, 32 byte lines 44h code and data L2 cache, 1024 KB, 4 ways, 32 byte lines 45h code and data L2 cache, 2048 KB, 4 ways, 32 byte lines 50h code TLB, 4K/4M/2M pages, fully, 64 entries 51h code TLB, 4K/4M/2M pages, fully, 128 entries 52h code TLB, 4K/4M/2M pages, fully, 256 entries 5Bh data TLB, 4K/4M pages, fully, 64 entries 5Ch data TLB, 4K/4M pages, fully, 128 entries 5Dh data TLB, 4K/4M pages, fully, 256 entries 66h data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored 67h data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored 68h data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored 70h trace L1 cache, 12 KμOPs, 8 ways 71h trace L1 cache, 16 KμOPs, 8 ways 72h trace L1 cache, 32 KμOPs, 8 ways 77h code L1 cache, 16 KB, 4 ways, 64 byte lines, sectored (IA-64) 79h code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored 7Ah code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored 7Bh code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectored 7Ch code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored 7Eh code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64) 81h code and data L2 cache, 128 KB, 8 ways, 32 byte lines 82h code and data L2 cache, 256 KB, 8 ways, 32 byte lines 83h code and data L2 cache, 512 KB, 8 ways, 32 byte lines 84h code and data L2 cache, 1024 KB, 8 ways, 32 byte lines 85h code and data L2 cache, 2048 KB, 8 ways, 32 byte lines 88h code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64) 89h code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64) 8Ah code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64) 8Dh code and data L3 cache, 3096 KB, 12 ways, 128 byte lines (IA-64) 90h code TLB, 4K...256M pages, fully, 64 entries (IA-64) 96h data L1 TLB, 4K...256M pages, fully, 32 entries (IA-64) 9Bh data L2 TLB, 4K...256M pages, fully, 96 entries (IA-64) 值 描述 70h Cyrix specific: code and data TLB, 4K pages, 4 ways, 32 entries 74h Cyrix specific: ??? 77h Cyrix specific: ??? 80h Cyrix specific: code and data L1 cache, 16 KB, 4 ways, 16 byte lines 82h Cyrix specific: ??? 84h Cyrix specific: ??? 值 描述 others 保留 举个例子有一块 P6 EAX=0302_0101h EBX=0000_0000h ECX=0000_0000h EDX=0604_0A43h 这块P6处理器包含4K/M code/data TLB,8+8 KB code/data L1 cache 和混合 512 KB code/data L2 cache. 说明 说明 #1 在多处理器系统中要特别注意,应该执行. EAX=0000_0003h 输入 EAX=0000_0003h 得到处理器序列号 #1 输出 EBX=xxxx_xxxxh 处理器序列号(只只是Transmeta Crusoe) ECX=xxxx_xxxxh 处理器序列号 EDX=xxxx_xxxxh 处理器序列号 说明 说明 #1 仅当PSN有效时. EAX= 8000_0000h 输入 EAX=8000_0000h 得到扩展CPUID指令所支持的最大值和厂家的名称字符串 输出 EAX=xxxx_xxxxh 最大值 EBX-EDX-ECX 厂家的名称字符串 AuthenticAMD AMD 保留 Cyrix 保留 Centaur 保留 Intel TransmetaCPU Transmeta 保留 National Semiconductor extended EAX= 8000_0001h 输入 EAX=8000_0001h 得到处理器 family/model/stepping and features flags #0 输出 EAX=0000_0xxxh 处理器 family/model/stepping family Family是 bits 11..8. 5 AMD K5 Centaur C2 Transmeta Crusoe TM3x00 and TM5x00 6 AMD K6 VIA Cyrix III 7 AMD K7 model model 是bits 7..4. AMD K5 1 5k86 (PR120 or PR133) 2 5k86 (PR166) 3 5k86 (PR200) AMD K6 6 K6 (0.30 μm) 7 K6 (0.25 μm) 8 K6-2 9 K6-III D K6-2+ or K6-III+ (0.18 μm) AMD K7 1 Athlon (0.25 μm) 2 Athlon (0.18 μm) 3 Duron (SF core) 4 Athlon (TB core) 6 Athlon (PM core) 7 Duron (MG core) 8 Athlon (TH core) A Athlon (Barton core) Centaur 8 C2 9 C3 VIA Cyrix III 5 Cyrix M2 core 6 WinChip C5A core 7 WinChip C5B core (if stepping = 0..7) 7 WinChip C5C core (if stepping = 8..F) 8 WinChip C5C-T core (if stepping = 0..7) Transmeta 4 Crusoe TM3x00 and TM5x00 stepping stepping是bits 3..0. Stepping的值是处理器的细节. EDX=xxxx_xxxxh feature flags description of indicated feature bit 31 (3DNow!) 3DNow! bit 30 (3DNow!+) extended 3DNow! bit 29 (LM) AA-64, Long Mode(也就是AMD的X86-64指令集) bit 28 保留 bits 27..25 保留 bit 24 (MMX+) bit 24 (FXSR) Cyrix specific: extended MMX AMD K7: FXSAVE/FXRSTOR, CR4.OSFXSR bit 23 (MMX) MMX b上一页 [1] [2] [3] [4] 下一页 没有相关教程
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